(China (Mainland))
Product Summary
The TB5R1LDWR is a quad differential receiver. It accepts digital data over balanced transmission lines. The TB5R1LDWR translates differential input logic levels to TTL output logic levels. The TB5R1LDWR is a pin- and function-compatible replacement for the Agere systems BRF1A and BRF2A; it includes 3-kV HBM and 2-kV CDM ESD protection. The TB5R1LDWR is suitable for Digital Data or Clock Transmission Over Balanced Lines.
Parametrics
TB5R1LDWR absolute maximum ratings: (1)Supply voltage, V CC: 0 V to 6 V; (2)Magnitude of differential bus (input) voltage: 8.4 V; (3)ESD, Human Body Model: ± 3 kV; Charged-Device Model: ± 2 kV; (4)Storage temperature, T stg: -65 to 150℃.
Features
TB5R1LDWR features: (1)Functional Replacements for the Agere BRF1A, BRF2A, BRS2A, and BRS2B; (2)Pin Equivalent to General Trade 26LS32; (3)High Input Impedance Approximately 8 kΩ; (4)4-ns Maximum Propagation Delay; (5)TB5R1 Provides 50-mV Hysteresis; (6)TB5R2 With -125-mV Threshold Offset for Preferred State Output; (7)-1.1-V to 7.1-V Common Mode Range; (8)Single 5-V ± 10% Supply; (9)Slew Rate Limited (1 ns min 80% to 20%); (10)TB5R2 Output Defaults to Logic 1 When In-puts Left Open or Shorted to V CC or GND; (11)ESD Protection HBM > 3 kV, CDM > 2 kV; (12)Operating Temperature Range: -40 to 85℃; (13)Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package.
Diagrams
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 TB5R1LDWR |
Texas Instruments |
LVDS Interface IC Hi Spd Diff Receiver |
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TB5R1 |
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TB5R1DE4 |
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TB5R1DR |
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LVDS Interface IC Quad PECL Line Receiver |
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TB5R1DRE4 |
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LVDS Interface IC Quad PECL Line Receiver |
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TB5R1DW |
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LVDS Interface IC Quad PECL Line Receiver |
Data Sheet |
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